The present invention relates to a semiconductor manufacturing technology; and, more particularly, to a method for manufacturing a semiconductor device for forming a landing plug.
As a semiconductor device is highly integrated, a landing plug process is generally performed before a contact process for securing sufficient process margin when forming a storage node contact plug of a bit line or capacitor.
Currently, in order to compensate for a thickness of a gate hard mask nitride layer in a landing plug contact (LPC) process of a 90-nm device, a buffer layer with poor step coverage is deposited with a predetermined thickness after etching the landing plug contact conventionally.
FIGS. 1A and 1B are sectional views illustrating a method for manufacturing a conventional semiconductor device.
Referring to FIG. 1A, a plurality of gate lines G are formed on a predetermined region of a substrate 11. Each of the gate lines G is configured with a gate insulating layer 12, a gate polysilicon layer 13, a gate tungsten silicide layer 14, and a gate hard mask nitride layer 15, which are stacked on the substrate 11 in sequence.
Thereafter, a gate spacer 16 and a cell spacer nitride layer 17 are deposited on the gate line G and the substrate 11.
Subsequently, after depositing an interlayer insulating layer 18 on the entire surface of the substrate 11 having the gate line G, an etching process for the landing plug contact is carried out to thereby form a contact hole 19 that opens respective areas over first and second junction regions A and B to be connected to a bit line contact (not shown) and a storage node contact (not shown), respectively.
Afterwards, a buffer oxide layer 20 with poor step coverage is deposited on the gate line G and the surface of the contact hole 19. For instance, the buffer oxide layer 20 is formed such that the buffer oxide layer 20 formed on the substrate 1 and sidewalls of the gate line G is formed thinly, whereas the buffer oxide layer 20 formed on the gate line G is relatively thick.
Next, referring to FIG. 1B, a cleaning process is performed to remove the buffer oxide layer 20 formed on the bottom surface of the contact hole 19, and thereafter, an etch-back process is performed on the buffer oxide layer 20 so as to open the first and second junction regions A and B.
However, according to the conventional method, since the cell spacer nitride layer 17 ad the gate spacer 16 are etched under the condition that an etch selectivity ratio between the oxide layer and the nitride layer is 1:1 in the etch-back process, a portion of the gate hard mask nitride layer 15 of the gate line G is simultaneously removed during the etch-back process, which is represented as X in FIG. 1B. This leads to a problem that a self-aligned contact margin decreases due to the etch loss of the gate hard mask nitride layer 15.